A processor controlled communication system may include one or more Processor Elements each including a central processing unit (CPU), one or more memory components and one or more input/output (I/O) components. Each memory component provides program and data storage while each I/O component interfaces the communication system to any of a variety of data handling devices. The total number of memories and I/O components within a Processing Element may not be known in advance nor is the ordering or physical location of these components within the Processing Element. Hence, the configuration of a Processing Element is not known, moreover, it can change from time to time. The configuration of a Processing Element can be readily ascertained when a data bus interconnects the CPU to all of the memories and I/O components. However, in some system architectures it is not cost effective to require complete connectivity (i.e., a data bus) between the CPU and the memory components and I/O components.
One such arrangement exhibiting incomplete connectivity includes a CPU connected over a CPU data bus only to the memories, while the memories are connected over a separate I/O data bus only to the I/O components. In that arrangement the CPU is only connected to the I/O components over an interrupt bus which does not support the transmission of arbitrary data thereover. Because the CPU does not have a data connection to the I/O components, a problem exists during power-up or initialization when the CPU has to identify I/O components and configure them into the system.